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gr2hw.h.z
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gr2hw.h
Wrap
C/C++ Source or Header
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1992-04-03
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15KB
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525 lines
#ifndef __SYS_GR2HW_H__
#define __SYS_GR2HW_H__
#ident "$Revision: 1.36 $"
/*
* HQ2 definition
*/
struct hq2 {
volatile unsigned long attrjmp[16];
volatile unsigned long version;
volatile unsigned long numge;
volatile unsigned long fin1;
volatile unsigned long fin2;
volatile unsigned long dmasync;
volatile unsigned long fifo_full_timeout;
volatile unsigned long fifo_empty_timeout;
volatile unsigned long fifo_full;
volatile unsigned long fifo_empty;
volatile unsigned long ge7loaducode;
volatile unsigned long gedma;
volatile unsigned long hq_gepc;
volatile unsigned long gepc; /*Used to load ge7 ucode*/
volatile unsigned long intr;
volatile unsigned long unstall;
volatile unsigned long mystery;
volatile unsigned long refresh; /* 0x6A080 */
volatile unsigned char pad0[3964];
volatile unsigned long fin3; /* 0x6B000 */
};
/*
* GE7 definition
*/
struct ge7 {
volatile unsigned long int ram0[256];
};
struct bdversion {
volatile unsigned char rd0;
unsigned char pad0[3];
volatile unsigned char rd1;
unsigned char pad1[3];
volatile unsigned char rd2;
unsigned char pad2[3];
volatile unsigned char rd3;
unsigned char pad3[19];
};
struct clock {
volatile unsigned char write;
unsigned char pad0[31];
};
/*
* VC1 definition
*/
struct vc1 {
volatile unsigned short cmd0;
unsigned char pad0[2];
volatile unsigned char xmapmode;
unsigned char pad1[3];
volatile unsigned short sram;
unsigned char pad2[2];
volatile unsigned char testreg;
unsigned char pad3[3];
volatile unsigned char addrlo;
unsigned char pad4[3];
volatile unsigned char addrhi;
unsigned char pad5[3];
volatile unsigned char sysctl;
unsigned char pad6[7];
};
/*
* BT479 definition
*/
struct bt479_dac {
volatile unsigned char wraddr;
unsigned char pad0[3];
volatile unsigned char paltram;
unsigned char pad1[3];
volatile unsigned char pixrdmsk;
unsigned char pad2[3];
volatile unsigned char rdaddr;
unsigned char pad3[3];
volatile unsigned char ovrlay_wraddr;
unsigned char pad4[3];
volatile unsigned char ovrlay;
unsigned char pad5[3];
volatile unsigned char ctl;
unsigned char pad6[3];
volatile unsigned char ovrlay_rdaddr;
unsigned char pad7[3];
};
/*
* BT457 definition */
struct gr2_bt457_dac {
volatile unsigned char addr;
unsigned char pad0[0x3];
volatile unsigned char paltram;
unsigned char pad1[0x3];
volatile unsigned char cmd2;
unsigned char pad2[0x3];
volatile unsigned char ovrlay;
unsigned char pad3[19];
};
/*
* XMAP5 definition
*/
struct xmap5 {
volatile unsigned char misc; /* Miscellaneous internal registers*/
unsigned char pad0[0x3];
volatile unsigned long mode; /* Mode registers*/
volatile unsigned char clut; /*Color Look Up Table */
unsigned char pad1[0x3];
volatile unsigned char crc; /*CRC and revision #, Read only */
unsigned char pad2[0x3];
volatile unsigned char addrlo;
unsigned char pad3[0x3];
volatile unsigned char addrhi;
unsigned char pad4[0x3];
volatile unsigned char bytecnt;
unsigned char pad5[0x3];
volatile unsigned char fifostatus;
unsigned char pad6[0x3];
};
/*
* GIO GR2 memory map
*/
struct gr2_hw {
volatile unsigned long int shram[32768]; /* shared data ram */
/* shared data ram only 32768 words*/
unsigned char pad[131072];
/* 0x1f000000 */
volatile unsigned long int fifo[32768]; /* fifo */
/* 0x1f040000 */
volatile unsigned long int hqucode[8192]; /* hq2 ucode */
/* 0x1f060000 */
struct ge7 ge[8]; /* ge7 RAM0*/
/* 0x1f068000 */
struct hq2 hq; /* hq2 internal registers */
/* 0x1f06a000 */
unsigned char pad0[4092];
struct bdversion bdvers; /* board version */
/* 0x1f06c000 */
struct clock clock; /* clock */
/* 0x1f06c020 */
struct vc1 vc1; /* vc1 */
/* 0x1f06c040 */
struct bt479_dac rd479dac; /* Read triple dac */
/* 0x1f06c060 */
struct bt479_dac wr479dac; /* Write triple dac */
/* 0x1f06c080 */
struct gr2_bt457_dac reddac; /* red 457 dac */
/* 0x1f06c0a0 */
struct gr2_bt457_dac grndac; /* green 457 dac */
/* 0x1f06c0c0 */
struct gr2_bt457_dac bluedac; /* blue 457 dac */
/* 0x1f06c0e0 */
struct xmap5 xmap[5]; /* xmap */
/* 0x1f06c100 */
struct xmap5 xmapall; /* xmap all */
/* 0x1f06c1a0 */
volatile unsigned long int video_ack[8]; /* video with ACK */
/* 0x1f06c1c0 */
volatile long int video_noack[8]; /* video without ACK */
/* 0x1f06c1e0 */
volatile long int re3_27bit[32]; /* 27-bit RE3 registers */
/* 0x1f06c200 */
volatile long int re3_24bit[96]; /* 24-bit RE3 registers */
/* 0x1f06c280 */
unsigned char pad9[512]; /* 0x1f06c400 */
volatile long int re3_32bit; /* 32-bit RE3 register */
/* 0x1f06c600 */
};
#ifdef IP17
#include <sys/mp_gio.h>
struct expgrinchmap {
struct gr2_hw gr2;
unsigned char _pad0[0x6d000-sizeof(struct gr2_hw)];
struct {
struct {
struct {
volatile unsigned long regab[0x800/sizeof(unsigned long int)];
volatile unsigned long regcd[0x800/sizeof(unsigned long int)];
} set;
struct {
volatile unsigned long regab[0x800/sizeof(unsigned long int)];
volatile unsigned long regcd[0x800/sizeof(unsigned long int)];
} go;
} int3way;
} threeway;
struct mg1_regs mg1;
};
#endif /* IP17 */
/*
* HQ2 constants
*/
#define HQ2_DMASYNC_INACTIVE 2
#define HQ2_FINISH1 0x4
#define HQ2_FINISH2 0x2
#define HQ2_FINISH3 0x1
/*
* GE7 constants
*/
/*
* VC1 constants
*/
/* Host Command */
#define GR2_VC1_CMD0 0x0
#define GR2_VC1_VID_TIMING 0x0
#define GR2_VC1_CURSOR_CTRL 0x0
#define GR2_VC1_DID_CTRL 0x0
#define GR2_VC1_XMAP_CTRL 0x0
#define GR2_VC1_XMAP_MODE 0x1
#define GR2_VC1_EXT_MEMORY 0x2
#define GR2_VC1_TEST_REGS 0x3
#define GR2_VC1_ADDR_LOW 0x4
#define GR2_VC1_ADDR_HIGH 0x5
#define GR2_VC1_SYS_CTRL 0x6
#define GR2_VC1_INTERRUPT 0x1 /* active low */
#define GR2_VC1_VTG 0x2 /* active low */
#define GR2_VC1_VC1 0x4 /* active high */
#define GR2_VC1_DID 0x8 /* active high */
#define GR2_VC1_CURSOR 0x10 /* active high */
#define GR2_VC1_CURSOR_DISPLAY 0x20 /* active high */
#define GR2_VC1_GENSYNC 0x40 /* active high */
#define GR2_VC1_VIDEO 0x80 /* active high */
/* Video Timing Generator */
#define GR2_VID_EP 0x00
#define GR2_VID_LC 0x02
#define GR2_VID_SC 0x04
#define GR2_VID_TSA 0x06
#define GR2_VID_TSB 0x07
#define GR2_VID_TSC 0x08
#define GR2_VID_LP 0x09
#define GR2_VID_LS_EP 0x0b
#define GR2_VID_LR 0x0d
#define GR2_VID_FC 0x10
#define GR2_VID_ENAB 0x14
/* Cursor Generator */
#define GR2_CUR_EP 0x20
#define GR2_CUR_XL 0x22
#define GR2_CUR_YL 0x24
#define GR2_CUR_MODE 0x26
#define GR2_CUR_BX 0x27
#define GR2_CUR_LY 0x28
#define GR2_CUR_YC 0x2a
#define GR2_CUR_CC 0x2e
#define GR2_CUR_RC 0x30
/* Display ID Generation */
#define GR2_DID_EP 0x40
#define GR2_DID_END_EP 0x42
#define GR2_DID_HOR_DIV 0x44
#define GR2_DID_HOR_MOD 0x45
#define GR2_DID_LP 0x46
#define GR2_DID_LS_EP 0x48
#define GR2_DID_WC 0x4a
#define GR2_DID_RC 0x4c
/* Control Register */
#define GR2_BLKOUT_EVEN 0x60
#define GR2_BLKOUT_ODD 0x61
#define GR2_AUXVIDEO_MAP 0x62
#define GR2_CURS_XOFF_1280 250 /* Horizontal Backporch - H60*/
#define GR2_CURS_XOFF_HZ72 240 /* Horizontal Backporch - H720*/
#define GR2_CURS_YOFF_1280 35 /* Vertical Backporch - H60*/
#define GR2_CURS_XOFF_NTSC 60 /* Horizontal Backporch - NTSC */
#define GR2_CURS_YOFF_NTSC 14 /* Vertical Backporch - NTSC*/
#define GR2_CURS_XOFF_PAL 90 /* Horizontal Backporch - PAL*/
#define GR2_CURS_YOFF_PAL 20 /* Vertical Backporch - PAL*/
/* Mode Register */
/* Even XMAP */
#define GR2_MODE_REG_0_E 0x00
#define GR2_MODE_REG_1_E 0x02
#define GR2_MODE_REG_2_E 0x04
#define GR2_MODE_REG_3_E 0x06
#define GR2_MODE_REG_4_E 0x08
#define GR2_MODE_REG_5_E 0x0a
#define GR2_MODE_REG_6_E 0x0c
#define GR2_MODE_REG_7_E 0x0e
#define GR2_MODE_REG_8_E 0x10
#define GR2_MODE_REG_9_E 0x12
#define GR2_MODE_REG_A_E 0x14
#define GR2_MODE_REG_B_E 0x16
#define GR2_MODE_REG_C_E 0x18
#define GR2_MODE_REG_D_E 0x1a
#define GR2_MODE_REG_E_E 0x1c
#define GR2_MODE_REG_F_E 0x1e
#define GR2_MODE_REG_10_E 0x20
#define GR2_MODE_REG_11_E 0x22
#define GR2_MODE_REG_12_E 0x24
#define GR2_MODE_REG_13_E 0x26
#define GR2_MODE_REG_14_E 0x28
#define GR2_MODE_REG_15_E 0x2a
#define GR2_MODE_REG_16_E 0x2c
#define GR2_MODE_REG_17_E 0x2e
#define GR2_MODE_REG_18_E 0x30
#define GR2_MODE_REG_19_E 0x32
#define GR2_MODE_REG_1A_E 0x34
#define GR2_MODE_REG_1B_E 0x36
#define GR2_MODE_REG_1C_E 0x38
#define GR2_MODE_REG_1D_E 0x3a
#define GR2_MODE_REG_1E_E 0x3c
#define GR2_MODE_REG_1F_E 0x3e
/* Odd XMAP */
#define GR2_MODE_REG_0_O 0x40
#define GR2_MODE_REG_1_O 0x42
#define GR2_MODE_REG_2_O 0x44
#define GR2_MODE_REG_3_O 0x46
#define GR2_MODE_REG_4_O 0x48
#define GR2_MODE_REG_5_O 0x4a
#define GR2_MODE_REG_6_O 0x4c
#define GR2_MODE_REG_7_O 0x4e
#define GR2_MODE_REG_8_O 0x50
#define GR2_MODE_REG_9_O 0x52
#define GR2_MODE_REG_A_O 0x54
#define GR2_MODE_REG_B_O 0x56
#define GR2_MODE_REG_C_O 0x58
#define GR2_MODE_REG_D_O 0x5a
#define GR2_MODE_REG_E_O 0x5c
#define GR2_MODE_REG_F_O 0x5e
#define GR2_MODE_REG_10_O 0x60
#define GR2_MODE_REG_11_O 0x62
#define GR2_MODE_REG_12_O 0x64
#define GR2_MODE_REG_13_O 0x66
#define GR2_MODE_REG_14_O 0x68
#define GR2_MODE_REG_15_O 0x6a
#define GR2_MODE_REG_16_O 0x6c
#define GR2_MODE_REG_17_O 0x6e
#define GR2_MODE_REG_18_O 0x70
#define GR2_MODE_REG_19_O 0x72
#define GR2_MODE_REG_1A_O 0x74
#define GR2_MODE_REG_1B_O 0x76
#define GR2_MODE_REG_1C_O 0x78
#define GR2_MODE_REG_1D_O 0x7a
#define GR2_MODE_REG_1E_O 0x7c
#define GR2_MODE_REG_1F_O 0x7e
/* Test Registers */
#define GR2_CRC_SYNDROME 0x00
#define GR2_CRC_CONTROL 0x03
#define GR2_CHIP_REVISION 0x04
#define GR2_TEMP_EVEN 0x80
/*
* BT479 constants
*/
#define GR2_BT_WRITE_ADDR 0
#define GR2_BT_PALETTE_RAM479 1
#define GR2_BT_PIXEL_READ_MASK 2
#define GR2_BT_READ_ADDR 3
#define GR2_BT_OVERLAY_WRITE_ADDR 4
#define GR2_BT_OVERLAY479 5
#define GR2_BT_CONTROL 6
#define GR2_BT_OVERLAY_READ_ADDR 7
/*
* BT457 constants
*/
#define GR2_BT_ADDR 0
#define GR2_BT_PALETTE_RAM 1
#define GR2_BT_CMD2 2
#define GR2_BT_OVERLAY 3
#define GR2_DAC_READMASK 0x4 /* offset of read mask */
#define GR2_DAC_BLINKMASK 0x5 /* offset of blink mask */
#define GR2_DAC_CMD 0x6 /* offset of command register */
#define GR2_DAC_TEST 0x7 /* offset of test register */
#define GR2_DAC_NGAMMAENT 256 /* Number gamma ramp entries */
#define GR2_DAC_NOVLMAPENT 4 /* Number overlay map entries */
/* DAC command register bit settings: */
#define GR2_DAC_5TO1MUX 0x80 /* use 5:1 multiplexing */
#define GR2_DAC_RAMENBL 0x40 /* Use RAM if over bits are 0 */
#define GR2_DAC_BLINK0 0x00 /* blink rate 0: 1.024(75/25) */
#define GR2_DAC_BLINK1 0x10 /* blink rate 1: 0.512(50/50) */
#define GR2_DAC_BLINK2 0x20 /* blink rate 2: 1.024(50/50) */
#define GR2_DAC_BLINK3 0x30 /* blink rate 3: 2.048(50/50) */
#define GR2_DAC_OL1BENBL 0x08 /* OL1 Blink Enable */
#define GR2_DAC_OL0BENBL 0x04 /* OL0 Blink Enable */
#define GR2_DAC_OL1ENBL 0x02 /* OL1 Enable */
#define GR2_DAC_OL0ENBL 0x01 /* OL0 Enable */
/*
* XMAP5 constants
*/
#define GR2_XMAP_MISC 0
#define GR2_XMAP_MODE 1
#define GR2_XMAP_CLUT 2
#define GR2_XMAP_CRC 3
#define GR2_XMAP_ADDRLO 4
#define GR2_XMAP_ADDRHI 5
#define GR2_XMAP_BYTECNT 6
#define GR2_XMAP_FIFOSTATUS 7
#define GR2_XMAP0 0
#define GR2_XMAP1 1
#define GR2_XMAP2 2
#define GR2_XMAP3 3
#define GR2_XMAP4 4
#define GR2_XMAPALL 10 /* !=5 to avoid possible incorrect numbering of xmaps*/
#define GR2_XMAP_NCOLMAPENT 8192 /* Number col map entries */
#define GR2_XMAP_NCOLMAP_VR 256 /* Number col map entries loaded during
one vertical retrace period */
#define GR2_XMAP_NMODEREGS 32 /* Number of entries in mode register
table */
#define GR2_XMAP_NAUXMAPENT 16 /* Number of auxiliary pixel planes*/
#define GR2_XMAP_NMULTIMAP 16 /* Number multimaps*/
/*
* XMAP mode register bit flags
*/
#define GR2_XMAP_POUMM_MASK 0x80 /* byte 0 */
#define GR2_XMAP_POUMD_MASK 0x60
#define GR2_XMAP_POUPG_MASK 0x1f
#define GR2_XMAP_POUPX_MASK 0x8000 /* byte 1 */
#define GR2_XMAP_POUOV_MASK 0x4000
#define GR2_XMAP_AUXPG_MASK 0x3E00
#define GR2_XMAP_ULENB_MASK 0x0100
#define GR2_XMAP_OVENB_MASK 0xf00000 /* byte 2 */
#define GR2_XMAP_VIDEO_MASK 0x0C0000
#define GR2_XMAP_PDMD_MASK 0x030000
#define GR2_XMAP_PIXPG_MASK 0xf8000000 /* byte 3 */
#define GR2_XMAP_PIXPG_SHIFT 27
#define GR2_XMAP_PIXMD_MASK 0x07000000
#define GR2_XMAP_PIXBNK_MASK 0x01000000
#define GR2_XMAP_POUBNK_MASK 0x8000
#define GR2_XMAP_AUXBNK_MASK 0x300000
/*
* XMAP mode register field value defines.
*/
#define GR2_XMAP_POUMM_ON 0x80
#define GR2_XMAP_POUMD_8BIT 0x20
#define GR2_XMAP_POUMD_4BIT0 0x40
#define GR2_XMAP_POUMD_4BIT1 0x60
#define GR2_XMAP_POUPX_8 0x00
#define GR2_XMAP_POUPX_16 0x8000
#define GR2_XMAP_POUOV_ON 0x4000
#define GR2_XMAP_POUUL_ON 0x0000
#define GR2_XMAP_ULENB_ON 0x0100
#define GR2_XMAP_OVENB_BIT0 0x100000
#define GR2_XMAP_OVENB_BIT1 0x200000
#define GR2_XMAP_OVENB_BIT2 0x400000
#define GR2_XMAP_OVENB_BIT3 0x800000
#define GR2_XMAP_VIDEO_OVL 0x040000
#define GR2_XMAP_VIDEO_UNL 0x080000
#define GR2_XMAP_VIDEO_RPL 0x0C0000
#define GR2_XMAP_PDMD_CI 0x000000
#define GR2_XMAP_PDMD_RGB 0x010000
#define GR2_XMAP_PDMD_MM 0x020000
#define GR2_XMAP_PDMD_BLK 0x030000
#define GR2_XMAP_PIXMD_4BIT0 0x00000000
#define GR2_XMAP_PIXMD_4BIT1 0x01000000
#define GR2_XMAP_PIXMD_8BIT0 0x02000000
#define GR2_XMAP_PIXMD_8BIT1 0x03000000
#define GR2_XMAP_PIXMD_12BIT0 0x04000000
#define GR2_XMAP_PIXMD_12BIT1 0x05000000
#define GR2_XMAP_PIXMD_16BIT 0x06000000
#define GR2_XMAP_PIXMD_24BIT 0x07000000
#define GR2_XMAP_PIX_BNK0 0x00000000
#define GR2_XMAP_PIX_BNK1 0x01000000
#define GR2_XMAP_POU_BNK0 0x0000
#define GR2_XMAP_POU_BNK1 0x8000
#define GR2_XMAP_AUX_BNK0 0x100000
#define GR2_XMAP_AUX_BNK1 0x200000
#endif /* __SYS_GR2HW_H__ */